Presentations

Towards Monolithic Quantum Processors in Production FDSOI CMOS Technology

12 December 2019 Invited lecture at the IEEE Circuits and Systems Society Santa Clara Valley Chapter, Santa Clara, CA, USA

This presentation will discuss the fundamental concepts and the feasibility of high-temperature (2-4 K) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm FDSOI CMOS technology. The beneficial aspects of the SiGe channel hole-spin qubit will be emphasized in comparison with its silicon-only electron-spin counterpart. It is also shown that, at 2 K, MOSFETs and cascodes can be operated as quantum dots in the subthreshold region, while behaving as classical MOSFETs and cascodes in the saturation region, suitable for qubits and mm-wave mixed-signal processing circuits, respectively. Challenges in the design and testing of quantum processor units monolithically integrated with readout and mm-wave spin control electronics in commercial 22nm FDSOI CMOS technology, will also be covered. Finally, I will present measurements for full technology characterization at cryogenic temperatures up to 67 GHz.

S. P. Voinigescu

Towards Monolithic Quantum Processors in Production FDSOI CMOS Technology

15 November 2019 Invited talk at the IEEE Microwave Theory and Technique Society Chapter, Irvine, CA, USA

This presentation will discuss the fundamental concepts and the feasibility of high-temperature (2-4 K) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm FDSOI CMOS technology. The beneficial aspects of the SiGe channel hole-spin qubit will be emphasized in comparison with its silicon-only electron-spin counterpart. It is also shown that, at 2 K, MOSFETs and cascodes can be operated as quantum dots in the subthreshold region, while behaving as classical MOSFETs and cascodes in the saturation region, suitable for qubits and mm-wave mixed-signal processing circuits, respectively. Challenges in the design and testing of quantum processor units monolithically integrated with readout and mm-wave spin control electronics in commercial 22nm FDSOI CMOS technology, will also be covered. Finally, I will present measurements for full technology characterization at cryogenic temperatures up to 67 GHz.

Testing Requirements for Emerging Single-Chip Cryogenic Mixed-Signal Quantum Processors in Production 22nm FDSOI CMOS Technology

14 November 2019 Invited talk at the International Symposium for Testing and Failure Analysis 2019, Portland, OR, USA

This presentation will discuss testing requirements and challenges for two mixed-signal quantum processor architectures based on charge and spin qubits, respectively, monolithically integrated with readout and microwave/mm-wave control electronics in commercial 22nm FDSOI CMOS technology, and intended for operation at 4-12 Kelvin. Both qubit schemes rely on minimum size MOSFETs and multi-gate cascodes operated in the subthreshold region for the quantum core. Qubit, circuit, and technology characterization on-die at cryogenic temperatures and up to 67 GHz will be discussed.

Quantum supremacy with a superconducting processor

11 November 2019 IQubits Seminar Series, University of Modena and Reggio Emilia, Modena, Italy

Google recently reported the achievement of quantum supremacy. The 54-qubit programmable processor has in fact performed, in 200 seconds, a calculation that would have taken the world’s most powerful supercomputer 10,000 years. In this seminar, I will discuss in some detail this breakthrough in the field of quantum computing, and will put it in the context of the current developments. In particular, I will focus on the present and near-future quantum devices, which - unlike the ultimate, general purpose quantum computer - are designed to perform well-defined computational tasks and to operate without error correction.

F. Troiani

Millimeter-Wave Integrated Silicon Devices: Active versus Passive - The Eternal Struggle Between Good and Evil

11 October 2019 Invited plenary presentation at IEEE International Semiconductor Conference 2019, Sinaia, Romania

With the extreme scaling, active devices in both CMOS and BiCMOS technologies have reached outstanding fT/fMAX, enabling an ever-increasing number of existing and emerging applications in the microwave and millimeter wave (mm-wave) frequency range. This paper addresses qualitative and quantitative aspects that may help to further unveil the impact of losses on the overall circuit performance and stimulate the adoption of effective loss-aware design methodologies. The results show how, in low power regime, the performances of mm-wave LNAs are dominated by losses in passive components. We also show how loss-aware design methodologies can mitigate the performance degradation due to passives, resulting as an important tool to get the full potential out of the active devices available today.

Towards Monolithic Quantum Processors in Production FDSOI CMOS Technology

10 November 2019 Invited plenary talk at IEEE International Semiconductor Conference 2019, Sinaia, Romania

This presentation will discuss the feasibility of high-temperature (2-4 K) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm FDSOI CMOS technology, and demonstrate the advantage of the SiGe channel hole-spin qubit over its silicon-only electron-spin counterpart. It is also shown that, at 2 K, MOSFETs and cascodes can be operated as quantum dots in the subthreshold region, while behaving as classical MOSFETs and cascodes in the saturation region, suitable for qubits and mm-wave mixed-signal processing circuits, respectively.

S. P. Voinigescu

Spin Cluster Qubits in Molecular and Semiconductor Systems

10 October 2019

I will overview the implementation of spin cluster qubits in molecular nanomagnets, and discuss the manipulation of scalar quantities induced by oscillating electric fields, through the modulation of the exchange interaction, the g-factor or the axial anisotropy. Unlike what happens in electron spin resonance, where the oscillating magnetic field induces transitions between different Zeeman levels, here one manipulates the spin within subspaces of given Sz. This allows to protect the qubits from the main decoherence mechanisms, such as those resulting from the hyperfine interactions. The connections with the semiconductor-based implementation of quantum computing will also be discussed.

F. Troiani

Epitaxy and polarization engineering for future III-Nitride heterostructure devices

09 October 2019 Invited plenary presentation at IEEE International Semiconductor Conference 2019, Sinaia, Romania

This presentation will review progress on two key aspects important for the realization of future III-Nitride based devices, which could benefit from this material family particular characteristics (large direct bandgap range from 0.65 to 6 eV and strong polarization fields). The first relates to epitaxy of alloys with compositions spanning the entire ternary range, while the second emphasizes the importance of correct polarization fields engineering. In the first part recent results, in understanding epitaxial surface kinetics of InGaN alloys and achievement of high quality films in the entire composition range, will be discussed. In the second part the importance of correct polarization engineering will be emphasized in two different types of device applications: photovoltaic devices and resonant tunneling diodes.

E. Iliopoulos

Towards Monolithic Quantum Processors in Production FDSOI CMOS Technology

27 September 2019 STMicroelectronics, Crolles, France

This presentation will discuss the feasibility of high-temperature (2-4 K) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm FDSOI CMOS technology, and demonstrate the advantage of the SiGe channel hole-spin qubit over its silicon-only electron-spin counterpart. It is also shown that, at 2 K, MOSFETs and cascodes can be operated as quantum dots in the subthreshold region, while behaving as classical MOSFETs and cascodes in the saturation region, suitable for qubits and mm-wave mixed-signal processing circuits, respectively.

S. P. Voinigescu

Towards Monolithic Quantum Processors in Production FDSOI CMOS Technology

23 September 2019 Short course talk at IEEE European Solid-State Circuits Conference 2019, Krakow, Poland

This presentation will discuss the feasibility of high-temperature (2-4 K) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm FDSOI CMOS technology, and demonstrate the advantage of the SiGe channel hole-spin qubit over its silicon-only electron-spin counterpart. It is also shown that, at 2 K, MOSFETs and cascodes can be operated as quantum dots in the subthreshold region, while behaving as classical MOSFETs and cascodes in the saturation region, suitable for qubits and mm-wave mixed-signal processing circuits, respectively.

S. P. Voinigescu

Engineering Solid-State Qubits Structures for High-Temperature Silicon Quantum Computing Through Multi-Scale Simulations

11 September 2019 Italian Quantum Information Science Conference 2019, Milan, Italy

Among the different possible physical platforms implementing Quantum Computing schemes, spin qubits in semiconductors provide several advantages: integration with electron/hole spin control/readout circuitry on the same die, scalability, long coherence times and fast qubit logics. The scaling of CMOS technology will enable tunneling-based coupled quantum-dots (QDs) devices to be operated at high temperatures. To achieve this goal, optimal structures must be identified and engineered through physics-based simulations. Ginestra™ - a commercial multi-scale device simulation software developed by Applied Materials - is an optimal test-bed for material characterization, simulation of electrical properties and device optimization.

Towards 2-4 K monolithic quantum processors with control and readout electronics in production 22nm FDSOI CMOS technology

19 June 2019 Invited talk at the Workshop on Cryogenic Electronics for Quantum Computing, FermiLab, Batavia, IL, USA

This presentation will discuss the feasibility of high-temperature (2-4 K) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm FDSOI CMOS technology, and demonstrate the advantage of the SiGe channel hole-spin qubit over its silicon-only electron-spin counterpart. It is also shown that, at 2 K, MOSFETs and cascodes can be operated as quantum dots in the subthreshold region, while behaving as classical MOSFETs and cascodes in the saturation region, suitable for qubits and mm-wave mixed-signal processing circuits, respectively.

Design Considerations for Spin Readout Amplifiers in Monolithically Integrated Semiconductor Quantum Processors

03 June 2019 Venue: IEEE Radiofrequency Integrated Circuits Symposium, Boston, MA, USA

The high frequency performance of all active and passive devices in a production 22nm FDSOI CMOS technology was measured up to 40 GHz over temperature down to 3.3 Kelvin, targeting applications in cryogenic and quantum computing ICs. It was found that the quality factor of the passives and the ft and fMAX of both p- and n-MOSFETs improved at 3.3 K. More importantly for circuit design, the peak-ft and peak-sub fMAX current densities, and the MOM capacitor and polysilicon resistor values show no variance with temperature. This information and the measured I-V characteristics of electron and hole single- and double-quantum dot structures, measured at 2 K and representative of qubits, were used to design monolithically integrated double quantum dots with readout transimpedance amplifiers output matched to 50 Ω. Transimpedance gain, S21, and bandwidth of 108 dBΩ, 19 dB, and 7.5 GHz, respectively, were measured at 300 K with only 4.5 mW power consumption and S22 < -10 dB up to 60 GHz.

M. J. Gong

Towards Monolithic Quantum Processors in Production FDSOI CMOS Technology

02 May 2019 GlobalFoundries, Malta, NY, USA

This presentation will discuss the feasibility of high-temperature (2-4 K) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm FDSOI CMOS technology, and demonstrate the advantage of the SiGe channel hole-spin qubit over its silicon-only electron-spin counterpart. It is also shown that, at 2 K, MOSFETs and cascodes can be operated as quantum dots in the subthreshold region, while behaving as classical MOSFETs and cascodes in the saturation region, suitable for qubits and mm-wave mixed-signal processing circuits, respectively.

S. P. Voinigescu

Si-Based Transistor and Analog-Mixed-Signal Circuit Scaling and the Natural Progression of Moore's Law to Silicon Quantum Computing at the Atomic Scale

14 August 2017 IEEE Solid-State Circuits Society Distinguished Lecture at Aarhus University, Denmark

This presentation will compare the high frequency performance scaling of SiGe HBTs and MOSFETs to 2-3nm gate length and beyond 2 THz transistor fMAX based on technology CAD (TCAD) and atomistic simulations. Characterization techniques and S-parameter measurements of state-of-the-art silicon MOSFETs, SiGe HBTs, and of a variety of HBT-HBT and for MOS-HBT cascodes from DC to 325 GHz will be discussed along with simulations of the scaling of analog and mixed-signal mm-wave benchmark circuit performance from the current to future technology nodes. Finally, we will take a look at the room-temperature operation requirements for coupled double quantum-dot Si qubits which rely on resonant tunnelling multiple- gate MOSFET structures with sub-5nm dimensions in all directions.

Contact information

PROJECT COORDINATOR

Prof. Domenico Zitoinfo@iqubits.eu+4593508581