Presentations

Tutorial on Integrated Devices, Circuits and Systems for Quantum Computing - IEEE ISCAS 2024, Singapore

This work investigates the implementation of microwave and mm-wave integrated circuits for control and readout of electron/hole spin qubits, as elementary building blocks for future emerging quantum computing technologies. In particular, it summarizes the most relevant readout and control techniques of electron/hole spin qubits, addresses the feasibility and reports some preliminary simulation results of two blocks: transimpedance amplifier (TIA) and pulse generator (PG). The TIA exhibits a transimpedance gain of 108.5 dBΩ over a −3dB bandwidth of 18 GHz, with input-referred noise current spectral density of 0.89 pA/√Hz at 10 GHz. The PG provides a mm-wave sinusoidal pulse with a minimum duration time of 20 ps.

This presentation will discuss the fundamental concepts and the feasibility of high-temperature (2-4 K) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm FDSOI CMOS technology. The beneficial aspects of the SiGe channel hole-spin qubit will be emphasized in comparison with its silicon-only electron-spin counterpart. It is also shown that, at 2 K, MOSFETs and cascodes can be operated as quantum dots in the subthreshold region, while behaving as classical MOSFETs and cascodes in the saturation region, suitable for qubits and mm-wave mixed-signal processing circuits, respectively. Challenges in the design and testing of quantum processor units monolithically integrated with readout and mm-wave spin control electronics in commercial 22nm FDSOI CMOS technology, will also be covered. Finally, I will present measurements for full technology characterization at cryogenic temperatures up to 67 GHz.

This presentation will discuss testing requirements and challenges for two mixed-signal quantum processor architectures based on charge and spin qubits, respectively, monolithically integrated with readout and microwave/mm-wave control electronics in commercial 22nm FDSOI CMOS technology, and intended for operation at 4-12 Kelvin. Both qubit schemes rely on minimum size MOSFETs and multi-gate cascodes operated in the subthreshold region for the quantum core. Qubit, circuit, and technology characterization on-die at cryogenic temperatures and up to 67 GHz will be discussed.

With the extreme scaling, active devices in both CMOS and BiCMOS technologies have reached outstanding fT/fMAX, enabling an ever-increasing number of existing and emerging applications in the microwave and millimeter wave (mm-wave) frequency range. This paper addresses qualitative and quantitative aspects that may help to further unveil the impact of losses on the overall circuit performance and stimulate the adoption of effective loss-aware design methodologies. The results show how, in low power regime, the performances of mm-wave LNAs are dominated by losses in passive components. We also show how loss-aware design methodologies can mitigate the performance degradation due to passives, resulting as an important tool to get the full potential out of the active devices available today.

I will overview the implementation of spin cluster qubits in molecular nanomagnets, and discuss the manipulation of scalar quantities induced by oscillating electric fields, through the modulation of the exchange interaction, the g-factor or the axial anisotropy. Unlike what happens in electron spin resonance, where the oscillating magnetic field induces transitions between different Zeeman levels, here one manipulates the spin within subspaces of given Sz. This allows to protect the qubits from the main decoherence mechanisms, such as those resulting from the hyperfine interactions. The connections with the semiconductor-based implementation of quantum computing will also be discussed.

Among the different possible physical platforms implementing Quantum Computing schemes, spin qubits in semiconductors provide several advantages: integration with electron/hole spin control/readout circuitry on the same die, scalability, long coherence times and fast qubit logics. The scaling of CMOS technology will enable tunneling-based coupled quantum-dots (QDs) devices to be operated at high temperatures. To achieve this goal, optimal structures must be identified and engineered through physics-based simulations. We use Ginestra™ - a commercial multi-scale device simulation software developed by Applied Materials - is an optimal test-bed for material characterization, simulation of electrical properties and device optimization.

This presentation will discuss the feasibility of high-temperature (2-4 K) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm FDSOI CMOS technology, and demonstrate the advantage of the SiGe channel hole-spin qubit over its silicon-only electron-spin counterpart. It is also shown that, at 2 K, MOSFETs and cascodes can be operated as quantum dots in the subthreshold region, while behaving as classical MOSFETs and cascodes in the saturation region, suitable for qubits and mm-wave mixed-signal processing circuits, respectively.

The high frequency performance of all active and passive devices in a production 22nm FDSOI CMOS technology was measured up to 40 GHz over temperature down to 3.3 Kelvin, targeting applications in cryogenic and quantum computing ICs. It was found that the quality factor of the passives and the ft and fMAX of both p- and n-MOSFETs improved at 3.3 K. More importantly for circuit design, the peak-ft and peak-sub fMAX current densities, and the MOM capacitor and polysilicon resistor values show no variance with temperature. This information and the measured I-V characteristics of electron and hole single- and double-quantum dot structures, measured at 2 K and representative of qubits, were used to design monolithically integrated double quantum dots with readout transimpedance amplifiers output matched to 50 Ω. Transimpedance gain, S21, and bandwidth of 108 dBΩ, 19 dB, and 7.5 GHz, respectively, were measured at 300 K with only 4.5 mW power consumption and S22 < -10 dB up to 60 GHz.

This presentation will compare the high frequency performance scaling of SiGe HBTs and MOSFETs to 2-3nm gate length and beyond 2 THz transistor fMAX based on technology CAD (TCAD) and atomistic simulations. Characterization techniques and S-parameter measurements of state-of-the-art silicon MOSFETs, SiGe HBTs, and of a variety of HBT-HBT and for MOS-HBT cascodes from DC to 325 GHz will be discussed along with simulations of the scaling of analog and mixed-signal mm-wave benchmark circuit performance from the current to future technology nodes. Finally, we will take a look at the room-temperature operation requirements for coupled double quantum-dot Si qubits which rely on resonant tunnelling multiple- gate MOSFET structures with sub-5nm dimensions in all directions.